ECE – GY 6403 Fundamentals of Analog Integrated Circuit Design
Fall Semester 2025
Project problem 1
Deliverables:
- Handwritten or computer typed solution for each problem showing your reasoning and calculations to get the results. Clearly state and justify any assumption you deemed necessary to get the result. There is no specific format to present your homework, but all the problems should be presented in just one file (.pdf, .doc, etc.). Keep your work organized and easy to follow.
- Answer all highlighted parts of project problem in a lab report.
Project problem:
For this problem, you will be implementing the Five-Transistor OTA in Cadence
Virtuoso and experimenting with its properties. This problem grade goes toward your project and not homework.
1) Start by creating a new library in Cadence Virtuoso and creating a new cell view. Alternatively, you can reuse the same library you used in the last homework assignment and create a new schematic cell view.
2) Create the Five-Transistor OTA schematic shown in Figure 1 below. Use low-voltage threshold VTL PMOS and NMOS transistors from the NCSUTechLib FreePDK45 library. Below is a table of keyboard hotkeys for the Virtuoso schematic viewer, which you should use in order to have an easier time creating the schematic.
Table: List of Cadence Virtuoso Schematic Hotkeys
Figure 1: Five-Transistor OTA in Cadence Virtuoso
3) For the OTA, set (W/L)1,2 = (5μm/1μm) and set (W/L)3,4 = (1μm/2μm). Set the bias current I0 to 10 μA. Set the supply voltage VDD to 1 V. Set the common mode voltage of M1,2 to VCM. You can do this by typing VCM in the DC voltage box. Cadence will recognize this as a variable when you start running simulations. For the current and voltage sources, use the idc and vdc instances from the analogLib library.
4) Open ADE L and setup the model libraries. Your simulation will not run if your model libraries are not setup! To do this go to Setup -> Model Libraries in the ADE L window. Then go to the folder /ALL_PDK/FreePDK45/ncsu_basekit/models/hspice/tran_models/models_n om. Highlight all models and click open. If successful, your model libraries should look something as shown in Figure 2 below.
Figure 2: Model Libraries Setup
5) In your ADE L window choose DC analysis as the analysis you want to run.
Figure 3: DC Analysis Setup
6) Right click on the design variables sub-window in ADE L and click on the copy from cellview icon. You should see the VCM variable from your schematic. Set this value to 500 mV. Your ADE L window should look as shown in Figure 4 below.
Figure 4: ADE L window setup for DC analysis
7) Run the DC analysis. A DC analysis tells Cadence to solve for the DC
biasing points of a schematic. This is often a useful first step analysis for making sure your design is biased correctly. Once the design has simulated, go to your schematic window, right-click anywhere on your screen and click on Annotate -> DC Operating Points. This will allow you to see the operating voltages and currents across your design.
Are all transistors operating in saturation? You can prove this by inputting the expressions OP(“Mx” “region”)
You can also view other DC parameters by going to the ADE L window and clicking on Results -> Print -> DC Operating Points. A blank window should appear. Click on any transistor in your schematic and the window should be populated with DC operating parameters for that instance. (See Figure 5 as an example).
Figure 5: DC Operating Parameters for transistor M1
The small signal transconductance of the transistor gm should be labelled as “gm” in the parameter table. The small signal output resistance, ro, is not listed in the table. Instead, Cadence uses the convention “small signal output transconductance” go = 1/ro . In the table this is shown as “gds” . To find ro, simply find gds in the table and take its reciprocal.
Record the gm and ro values for each of the transistors in the schematic.
8) Now in your schematic change the voltage entering the gate of M1 to
VCM+Vin and the voltage entering the gate of M2 to VCM-Vin. Cadence will recognize the plus and minus signs as operations to be done on variables. Copy the Vin variable into your ADE L cellview. Open the DC analysis setup window and sweep Vin from 0 V to 500 mV while keeping VCM equal to 500 mV (Figure 6). The DC analysis in Cadence allows users to sweep a variable and observe how other DC parameters change in a design in response to that swept variable. Here, you will be observing the large signal behavior. of the OTA as Vin is swept.
Figure 6: DC Sweep Setup
9) Open the calculator by clicking on Tools -> Calculator in the ADE L window (Figure 7). The calculator is a graphical tool useful for plotting certain expressions in the design. In the calculator tool select the drain currents of M1 and M2 to be plotted. Alternatively, you can also edit these expressions directly in the ADE L window as you did in the previous homework.
Figure 7: Calculator Tool
After rerunning the simulation, submit plots of your swept drain currents for M1 and M2. (Note that you can apply markers to your plot using the m hotkey). Explain in your own words why the drain currents are what they are.
Now submit a plot of the voltage at the gates of M3 and M4. Explain why this voltage changes the way it does when Vin is swept. (Hint: use Vs in order to record swept voltages)
10) You will now run a transient analysis on the design. A transient analysis
allows you to view various signals in the design as they change with time.
Remove the vdc voltage sources and replace them with vsin sources from the analogLib library. Set the DC voltage to VCM, the amplitude to 100 μV and the frequency to 1 kHz. Make sure to change the amplitude to -100 μV for the gate of M2 . Your schematic should look as shown in Figure 8. Go to your ADE L window and add the transient analysis. Set the stop time to 4 ms. Set the accuracy to conservative (Figure 9). A conservative accuracy is more accurate than moderate and liberal but takes longer for the simulation to run. For larger designs, moderate and liberal accuracies are sometimes used in order to speed up tool runtime at the cost of accuracy.
Figure 8: Schematic of Five-Transistor OTA for Transient Analysis
Figure 9: Transient Setup
Submit a plot of the Differential Input (Vin+ - Vin-) and the output voltage vout in the same window. Using markers, compute the small signal voltage gain of the amplifier directly from your diagram. (See Figure 10 on how to split various graphs in the same window)
Figure 10: Example of a plot with output signals
Now do hand calculations to see what the theoretical small signal voltage gain of the OTA should be. You may use the values of gm and ro you obtained from Cadence in the previous part. Does your theoretical gain match your actual gain?
In your plot of vout, you will notice that the output signal has the same phase as Vin+ - Vin-. Briefly explain why this is the case and why the output is not inverted. How would you modify the design in order to have an inverted output signal (ie a phase of 180o)?
Now change the amplitude of your input sinusoid to 1 mV from 100 uV. You will notice that the output sinusoid is distorted. Submit a plot of your input differential signal and distorted output. Explain why the output waveform is distorted in terms of voltage swing.
Change the (W/L)3,4 to 1μm/1μm. You will notice that the output voltage swing is improved. Explain why increasing the (W/L) of transistors M3 and M4 improves the swing for this particular design.
Return (W/L)3,4 to 1μm/2μm. Change the transistor widths of M1 and M2 from 5 μm to 1 μm. Rerun the transient simulation. Submit a plot of your differential input and output signal. How has the small signal voltage gain changed?
Explain why it changed the way it did.
11) Modify the Five-Transistor OTA schematic to that shown in Figure 11 below.
Figure 11: Schematic of 5-transistor OTA for Problem 4
For this part, we will be using AC analysis. The AC analysis in Virtuoso allows you to calculate voltages and currents throughout a schematic as a function of frequency. Set the AC magnitude of the V1 voltage source to 1 V and the AC magnitude of the V2 voltage source to 0 V. Open the ADE L window and add the AC analysis in your simulator setup window. Set the sweep variable to frequency and the sweep range from 1 Hz to 1 GHz. Set the sweep type to logarithmic with 100 points per decade, see Figure 12.
Figure 12: AC Analysis Setup
Open the calculator to add the expressions dB20(VF(“/vout”)) and phase(VF(“/vout”)) to the outputs in your ADEL window. The VF function calculates the AC voltage at a node in the circuit. In this example we are looking at the AC voltage at the output of the OTA after applying a 1 V AC signal at the input, Vin+. Note, that the AC analysis in Cadence does not take voltage swings into account. Hence the value of VF(“/vout”) can exceed the maximum output voltage swing of the OTA. The input is set to 1 V in this case so that the VF(“/vout”) also simultaneously represents the gain of the amplifier since VF(“/vout”)/1 V = VF(“/vout”). The functions dB20() and phase() are special functions that compute a result in decibels and the phase of an AC expression, respectively.
Run the simulation. You should see bode plots of the magnitude and phase of the OTA. Submit the Bode plots of your magnitude and phase.