EEEE1004 – Summer Resit Coursework #2

Simulation and design of Op-Amp circuits using LTspice

In this coursework you will design and simulate some of the op-amp circuits that have been covered in the module (EEEE1004). This work will be anonymously marked so please do not put your name, or student ID number on the report or your circuits.

This coursework forms 15% of the mark for the EEEE1004 module.

Submission

Your coursework submission will consist of a report (a single PDF file - it suggested that this is created using Microsoft Word), containing your working for each of the questions, and 6 .asc files containing the simulation files for each question. The individual .asc files (which contain your circuits) that you have created while doing your coursework must be submitted. These files will be marked by automation of the simulation process and must be named in the following format “Question X.asc”, with X being the question number that it relates to, for example, ‘Question 1.asc’. The filename you should use for the question is highlighted next to the question.

Ensure that you label the nets as described in the question. Failure to do so will limit how many marks you will receive.

How will this work be marked

As part of the automation of the simulation used for marking, different input voltages and currents will be set and voltages and currents around the circuit will be checked to ensure they match those expected from the input parameters given in the task.

Full marks will be given to for a task if the simulation meets the requirements given in the question, this includes using the labels and device names described in the text.

If the simulation does not meet the requirements, then partial marks are available.

The working presented in your document is worth 50% of the marks, with the simulation aspect being worth the other 50%.

As mentioned above, the simulation files will be marked by automating the simulation process. Any deviation from using the labels and device numbering required will require manual intervention and the loss of one mark per intervention required (down to 50% of the question mark – ie down to 0% for the simulation aspect of the question).

If you show clear and correct working as part of your submission, but fail to submit a working simulation file, the marks will be limited to 50% of the marks available for that question.

Partial marks will also be given for your working up to 50% of the marks available for that question.

If the simulation presented matches your working, but your working is incorrect, the maximum mark available for the simulation part of the question will not be greater than the marks obtained from the working.

If an incorrect amplifier type is demonstrated a mark of zero will be awarded for that question.

You should assume that any value of resistance is available and must not limit yourself to using Standard Resistor Values.

It is anticipated that you will check that the simulated circuit you have produced meets the design requirements given in the question, that is you can check your own work meets the design requirements before submission through simulation.

Note: You are simulating a real op-amp (rather than an ideal one) and therefore the output values will not be exactly what you expect but will very close to the expected output – within 0.02%. Do not try to adjust your resistor values away from the theoretically correct values to get a perfect result.

Hints

Sometimes hints/reminders are given on how to achieve a task using LTspice, for example labelling a net. The keyboard shortcut will be shown like so, F4, meaning the F4 key on the keyboard should be pressed. How to achieve the same task using the menu bar may also be given, for example “Edit→Label Net”, means click on ‘Edit’ on the menu bar followed by ‘Label Net’.

Tasks

For each task, show your working in your document. You do not need to use an equation editor or similar, so long as the mathematics presented is clear and easy to follow. Suitably cropped photos/scans of handwritten equations inserted into the document are acceptable.

When an op-amp is required, only use the LT1097 Op-Amp (this can be found as a component in the ‘Opamps’ folder in the ‘Select Component Symbol’ window, found using F2 or “Edit→Component”) for this coursework.

Unless specified, for each task, the circuit needs to be powered appropriately, you should assume that the output voltages will never be outside the range of ±10V.

More than one op-amp might be required to complete some tasks. These must all be powered by named nets from the same pair of power supplies.

For all circuits the positive power supply voltages should be named V1 and the negative supply named V2. They should be connected to the correct pins on the op-amps via named nets, named V+ (for the positive supply) and V- (for the negative supply).

1. Design an op-amp circuit that will take a voltage as an input and will amplify it with a gain of -160.

The input voltage source must be named V3.

The named net for the input voltage should be Vin and named net for the output voltage must be Vout.  [Question 1.asc, 10 marks]

2. Design an op-amp circuit that will take a current as an input and will amplify it with a gain of 6250 Ω. You will need to add a current source to the circuit to demonstrate it working.

The conventional current should flow towards ground from the current source.The current source should be labelled I1. The net for the output voltage must be labelled Vout.   [Question 2.asc, 10 marks]

3. Design an op-amp circuit that will take a voltage as an input and will amplify it with a gain of 43. The magnitude of the current that flows through the feedback resistor must be between 0.2 mA and 2 mA when the output from the amplifier is the maximum voltage possible (for your power supply voltages).

The input voltage source must be named V3.

The named net for the input voltage should be Vin and named net for the output voltage must be Vout. The feedback resistor must be named Rf.  [Question 3.asc, 20 marks]

4. Design a circuit that takes 3 voltages as inputs (a, b, and c) which has an output that is equal to -5(3a + 5b) - 13c.

The three voltages sources used for the input voltages should be named VA, VB and VC and they should be connected to your circuit via named nets, named Va, Vb and Vc.  [Question 4.asc, 20 marks]

5. Create a voltage source labelled V3 and connect the positive terminal to a named net called Vin.

Set a source resistance for the voltage source by right clicking on it and entering a value into the Series Resistance box.

Figure 1: Setting the Series Resistance of V3 (for example to 2000 ohms).

The value you use should be between 1000 and 10000 ohms.

This setting will give the voltage source an output resistance. Looking from the point of view of an amplifer with an input of Vin, this is the also the source resistance.

Design a circuit that will amplify the signal Vin with a gain of 33.8 dB.

The gain of the circuit must not depend upon the value of Series Resistance chosen above. That is, if the Series Resistance is changed, the value of the output voltage should remain the same or almost identical.

The named net for the input voltage should be Vin and named net for the output voltage must be Vout.

Only use integer (whole number) values of Ohms for your resistances (round the value you require to 0 decimal places).   [Question 5.asc, 20 marks]

6. Design a circuit where the output voltage will be the difference between two input voltages, connected by named nets Va and Vb (the sources to be named VA and VB respectively), multiplied by 180. The output, Vout, should be 180 (Vb - Va). The output should also be independent of the source resistances of the inputs (see Figure 1 for setting source resistances). It is also a requirement that the gain of the circuit be adjustable using only one resistor, which must be labelled Rg. The named net for the output voltage must be Vout. The common mode rejection ratio (CMRR) must be infinite.   [Question 6.asc, 20 marks]