DEPARTMENT OF ELECTRICAL AND ELECTRONIC ENGINEERING

HDL FOR PROGRAMMABLE DEVICES

MODULE CODE: EEEE4123

Resit Project - Matrix Processing Core Design

1     INTRODUCTION

Matrix calculation is one of the fundamental mathematic calculations commonly used in advanced signal processing algorithms for a wide range of applications, such as satellite navigation systems, complex control systems and etc. In order to implement such advanced signal processing algorithms on an FPGA based embedded system, we need to use VHDL to design a matrix processing core for  an AMD FPGA device.

2     PROJECT DESCRIPTION

In this project, you are asked to develop a synthesisable matrix processing core, which is able to do matrix multiplication and addition (Fig. 1) for matrixes with the size of 32 x 32 and an 16-bit signed integer for each element of the input matrixes (A, B and C), and then implement the core on an AMD FPGA device with your choice. You are required to use behavioural simulation to verify your matrix processing core.

Fig. 1 Matrix Multiplication and Addition

The Matrix processing Core as shown in Fig. 2 mainly consists ofa signed multiplier, two signed  adders, three input buffers (InputBufferA, InputBufferB and InputBufferC) and one output buffer  (OutputBufferD). All these four buffers are simple dual-port block memories with part A for write and port B for read, which are created by using Xilinx core generator. Those three input buffers have the same size of 1024 x 16 bits, which are used to receive the data for matrix A, matrix B and matrix C, respectively. The output buffer has a size of 1024 x 64 bits, which is for the results of the matrix calculation. The data organisation of these four buffers is shown in Fig. 3.

Fig. 2 Matrix Processing Core

Fig. 3 Buffer Data Organisation

Write/Read timing requirements are shown in Fig. 4 and Fig. 5, respectively. In order to write a data to a particular address of the dual-port RAM, the valid data and address to be written must be presented at the signals, ‘dina’ and ‘addra’ at the rising edge of the clock with ‘1’ for signal ‘wea’ at the same rising edge. From the read operation, the address to be read must be presented at signal, ‘addrb’ at the rising edge of the clock with ‘1’ for signal ‘enb’ at the same rising edge. The read data will be available at signal ‘doutb’just after the rising edge.

Fig. 4 Timing for Write Operation to the Dual-Port RAM

Fig. 5 Timing for Read Operation to the Dual-Port RAM

3     DESIGN TASKS

Design a synthesisable matrix processing core and its testbench.

The specific design requirements are as follows:

•  To facilitate the assessment of your matrix processing core design, you must use the following entity declaration for the top level design.

-- Required entity declaration

entity IntMatProCore is

port(

Reset, Clock, WriteEnable:in std_logic;

-- BufferSel: "00" for input buffer A, "01" for input buffer B, "10" for input buffer C

BufferSel:    in std_logic_vector (1 downto 0);

WriteAddress: in std_logic_vector (9 downto 0);

WriteData:    in std_logic_vector (15 downto 0);

ReadAddress:  in std_logic_vector (9 downto 0);

ReadEnable:   in std_logic;

ReadData:     out std_logic_vector (63 downto 0);

DataReady:    out std_logic

);

end IntMatProCore;

•  In the testbench, you must use VHDL file I/O to read the data for three input matrixes from three input text files (inputA.txt, inputB.txt and inputC.txt) and then feed them to the design. Once the matrix calculation is completed, you must read out the results from the output buffer, compared with the output data (outputD_matlab.txt) from your Matlab model and write output data from your VHDL simulation and the comparison results into an output text file (outputD.txt). Please refer to the reference design provided.

•  The testbench must produce all the input signals and the simulation waveforms must show how the data of the matrixes A/B/C are written into the input buffers and how the matrix calculation results are read out from the output buffer.

•  The description of interface signals:

4 REFERENCE DESIGN

To get your VHDL project design started easily, a synthesisable matrix multiplier core design is provided as a reference design (Fig. 6/Fig. 7),  which is able to do matric multiplication for matrixes with the size of 4 x 4 and an 8-bit signed integer for each element of the input matrixes (A and B). The data buffers will be organised as Fig. 8.

Fig. 6 Matrix Multiplication

Fig. 8 Memory buffer organisation for the matrix multiplier core

5     DESIGN TOOLS

The project design tools is Xilinx Vivado WebPACK 2018.3.

6     PROJECT SUBMISSION

The VHDL project must be submitted on Moodle by 3:00pm, Monday, 11th August 2025. The submission must have a single zip file with a name of student name_student ID.zip, which includes the following:

•  A word file - 10-page project report

•  VHDL source codes

•  Matlab codes

•  inputA.txt, inputB.txt, inputC.txt - Input test data generated from your Matlab model

•  outputD_matlab.txt - Output test data generated from your Matlab model

•  outputD.txt - Output data produced from your VHDL testbench and the comparison result between the output data from your Matlab model and the output data from your VHDL simulation

•  Any other relevant files

• Entire Vivado project folder for your VHDL project design

The marking scheme of the VHDL project is as follows:

•  Design, Implementation and Verification (50%): It assesses:

o Matlab Model with signed integers

o VHDL code compilation

o Behavioural simulation

o Synthesis

o Coding quality

o Design efficiency

•   10-page report (50%): It should cover:

o Part 1

Current AMD FPGA technology review (up to 2 pages)

o Part 2

Description of project design

Simulation  including  a  few  simulation  waveforms  to  justify  your  design verification

Project discussion including the reason why you have chosen a particular FPGA device for your design

Conclusions

Further work

NOTE:      A penalty of 5% per working day will be imposed for the late submission.