Department of Electrical Engineering and Electronics
ELEC373
Digital Systems Design
Assignments 1 and 2
Random Number Generator
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Module
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ELEC373
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Coursework name
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Assignment 1 and Assignment 2
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Component weight
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Assignment 1 = 15%, Assignment 2 = 25%
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Semester
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1
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HE Level
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6
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Lab location
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PC labs 301, 304 as timetabled, at other times for private study
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Work
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Individually
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Timetabled time
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12 hours (3 hours per week - Wednesday 2pm - 5pm)
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Suggested private study
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10 hours including report writing
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Assessment method
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Individual, formal word-processed reports (Block diagrams and ASMs can be hand drawn and scanned into the report)
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Submission format
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Online via CANVAS
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Submission deadline
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Assignment 1: 23:59 on Sunday 17th November 2024
Assignment 2: 23:59 on Sunday 9th February 2025
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Late submission
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Standard university penalty applies
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Resit opportunity
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August resit period (if total module failed)
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Marking policy
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Marked and moderated independently
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Anonymous marking
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Yes
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Feedback
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Via comments on CANVAS
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Learning outcomes
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LO1: Ability to design digital systems using the ASM design method
LO2: Ability to implement digital systems using the Verilog Hardware Description Language
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ELEC 373 Verilog Assignments 1 & 2 (2024-2025)
Assignment Overview
These assignments have been set to get you familiar with designing digital systems and synthesising them from a Verilog description. You should develop your design using Altera’s Quartus II V13.0-SP1.
The first assignment is for you to undertake the first two stages of the design process i.e. the conceptual design, communicated by block diagrams, and the embodiment design communicated by ASM charts. You will also be coding some blocks in Verilog and simulating them to prove they function correctly.
The second assignment will require you to develop the full system in Verilog to prove that it works, although you can use a “bdf” file to connect your blocks together. You will be allowed to modify your design based on the feedback from the first assignment. You will test your design on a DE2 board in the EEE Department.
Assignments Outline
Many games of chance require a random number as input, be it from the throw of a dice or a ball on a roulette wheel. Your objective is to develop a design which will display random decimal numbers on the 7 segment displays of the DE2 board. For this example we will use the numbers as our selection for the national lottery where the choice of numbers starts at 1 and goes up to the last two digits of your University ID (add 20 to this number if the last two digits of your number are less than 30).
Your system operation should be as follows:
1. The operator presses KEYV to start the sequence.
2. The operator then presses KEYW and the first number is displayed on HEXX for Y seconds.
3. The system then starts counting again and the operator repeats stage 2. However, note that a number previously selected can’t be selected again.
4. The process is repeated until the number of numbers selected is equal to Z1. Remember that you should be careful about how you handle asynchronous inputs.
Report - Assignment 1
Your report should include the following.
1. Description of Architecture(s) and Controller(s) (with block diagrams showing interconnections).
2. ASM Charts for all Algorithmic State Machines. (1 page per ASM)
3. Commented Verilog code for each module for the Seven Segment Decoder and any counters you have in your design.
4. Full simulations of the Seven Segment Decoder and any counters you have in your design, with annotations indicating what the simulation proves.
5. Photographs of the 7 segment decoders working.
6. Discussion and Conclusions about the design choices made.
You should also submit your design and report via CANVAS. Make sure all the files need to compile, simulate and test the modules under Quartus 13.0SP1 are included in a single zip file. The report should be attached as a separate Word file. You should structure your report about each module, i.e. include ASM, then, where appropriate, Verilog code, then simulation results consecutively for each module rather than grouping all the ASMs together. All pages should be at the correct orientation for reading on a monitor. Report - Assignment 2
Your report should include the following.
1. Description of Architecture(s) and Controller(s) (with block diagrams showing interconnections).
2. ASM Charts for all Algorithmic State Machines. (1 page per ASM)
3. Commented Verilog code for each module.
4. Full simulations for each module you have in your design, with annotations indicating what the simulation proves.
5. RTL Schematic of the full system.
6. Simulation of the full system. (With annotations and maximum ½ page on any comments)
7. Photographs of the system in operation.
8. Explanation of experimental test results. (Max 1 page) Is it truly random?
9. Conclusion (Maximum ½ page)
10. Signed demonstrators check sheet if you design has been checked
You should also submit your design and report via CANVAS. Make sure all the files need to compile, simulate and test the design under Quartus 13.0SP1 are included in a single zip file. The report should be attached as a separate Word file. You should structure your report about each module, i.e. include ASM, then Verilog code, then simulation results consecutively for each module rather than grouping all the ASMs together. All pages should be at the correct orientation for reading on a monitor.
Warning
When marking the reports I will be looking very closely for any signs of collusion, as this is unacceptable. I need to assess your own ability not that of your friend or colleague. If I find any evidence of collusion then the formal University rules will be followed which may result in your suspension.
Assignment 1 Submission Deadline
You only need to submit an Electronic copy: Sunday 17th November 2024 @ 11:59pm. You also need to submit a ZIP file of your modules by the same date and time.
Assignment 2 Submission Deadline
You only need to submit an Electronic copy: Sunday 9th February 2025 @ 11:59pm. You also need to submit a ZIP file of your modules by the same date and time.
Hint
The challenging part to this assignment is preventing duplicate numbers being generated. However, you will get more marks for a working system that does generate duplicate numbers than for one that fails to work whilst attempting to eliminate duplicate numbers.