ELEC3207/ELEC6256: Nanoelectronic Devices

ELEC3207 and ELEC6256 Coursework

MOSFET Simulation Exercise

2025

Computer aided design plays a crucial role in the multi-billion-pound semiconductor industry. At the device engineering stage Technology Computer Aided Design (TCAD) is prevalent. It helps engineers optimize process flows and device characteristics prior to fabrication. TCAD can predict the electrical, optical, thermal and mechanical properties under set operating conditions given the data is properly calibrated. TCAD is purely physics based - using fundamental physical models such as drift-diffusion and Poisson equations to simulate the behaviour of devices.

For this coursework assignment, you will use the Silvaco TCAD package hosted on Iridis5, one of the University of Southampton s powerful high-performance computing facilities, to investigate metal oxide semiconductor field effect transistors (MOSFETs). You will be set a series of tasks that involve running simulations in TCAD to extract information about the structure and performance of these devices. You will write and submit a report on your work for assessment, which will contribute 30% of the marks for ELEC3207/ELEC6256.

Submit your report via handin.ecs.soton.ac.uk by 4 pm on Wednesday 3rd December 2025.

Aims and learning outcomes

This coursework exercise aims to give you experience in simulating MOSFET devices with a commonly-employed and well-established implementation of technology computer-aided design (TCAD). This  will allow you to deepen your understanding of the operation principles of MOSFETS as well as giving  you experience in using a set of industry standard simulation tools.

Having successfully completed this coursework assignment, you will be able to:

• Understand the operation principles of CMOS transistors

• Describe the differences between simple analytical models of devices and rigorous numerical  simulations

• Simulate the performance of CMOS transistors using Silvaco TCAD

• Vary process parameters to control device characteristics

Outline

Numerous commercial TCAD packages are available including Synopsys, Silvaco, Crosslight and  Cogenda. One of the leading implementations of TCAD used throughout the world is Silvaco TCAD. The package consists of several tools: a graphical user interface (GUI) called Deckbuild, a process  simulator called Athena, a device simulator called Atlas and finally a plotting tool called TonyPlot.

Athena models the various fabrication steps involved in semiconductor processing such as material  deposition, diffusion and etching, using various meshing strategies to generate a mixed grid element  mesh. This is advantageous as 2D structures can be formed from material growth and etching rather  than explicit geometry definition. This allows a means of forming complex 2D structures through  lithography steps followed by impurity diffusion as a function of time and temperature - key  processing steps that are common to device fabrication.

Atlas simulates the electrical behaviour in a semiconductor device that is represented as a mesh grid  file. Differential equations describing the electric potential and carrier distributions are applied to  each element of the mesh, with boundary conditions (i.e. potentials) provided at each electrode. The  equations are then solved to find the potential and carrier concentrations in each element. The  software uses a numerical solver which iterates repeatedly until a solution converges to a given  accuracy.

You will use example files supplied by Silvaco for modelling an n-type MOSFET with a polysilicon  gate. You should first become familiar with the operation of the simulation before tackling a series  of tasks that require you to make modifications to the scripts and carry out further analysis on the  results. Note that for Part II, the tasks you should complete depend on which version of the module  you are taking (ELEC3207 or ELEC6256). As such, please ensure you do the version of Part II for the  module you are taking.

Getting Started

Before starting the coursework simulation tasks, please work through the “Silvaco TCAD: Getting Started” document provided on the module notes page.

Simulation Tasks

Once you have familiarized yourself with the operation of Silvaco TCAD, you will be ready to tackle the following tasks. Please also refer to the helpful hints given later in this document.

IMPORTANT:

Try to limit yourself to a maximum of 2 TonyPlot windows and 1 DeckBuild window open at any one time to ensure that we do not use up all the available licences!

Part I MOSFET Data Extraction

***For all students***

(a)  Run the MOSFET example given by Silvaco (mos1ex01.in) to extract from the I-V curves the following parameters:

i.       on current (Ion) (when Vg=3 V)

ii.       off current (Ioff)

iii.       threshold voltage (Vth)

iv.       sub-threshold swing (S)

(b)  Extract the following physical device parameters:

i.       gate oxide thickness

ii.       body doping

iii.       gate material

iv.       gate doping

v.       gate length

The width in this two-dimensional simulation is 1 μm.  Extraction can be performed using simulation commands or by reading values from graphs in TonyPlot.

(c)   Re-run the simulation with drain voltage at 3V (see helpful hint 1 on how to do this) and extract the on current (when Vg=3 V).

(d)  Use theoretical (analytical) MOSFET formulae, together with the extracted physical device parameters and an appropriate value of mobility, to calculate the following I-V parameters:

i.        Ion, Ioff, Vth  and S at a drain voltage (Vd) of 0.1 V

ii.        Ion for Vd  = 3 V

(e)  Compare the values calculated from MOSFET formulae with the I-V parameters extracted from the simulation, explaining any differences you observe.

Part II for ELEC3207 students     Mobility and Velocity Saturation

***Only for students taking ELEC3207***

(a)  Continuing with the mos1ex01.in example script, alter the script. to replace the process

simulation (Athena) with its structure file so that you do not have to re-run that part of the simulation over and over again (see helpful hint 2). Add the following statement in the device simulation (Atlas) section, immediately below the models cvt srh print statement:

mobility mumaxn.cvt=1500

This makes the low field electron mobility of the Si explicit (and sets it to 1500 cm2/Vs).

Change the low field electron mobility and re-run the simulation to obtain the Id-Vg  output  characteristics.  Do this for a range of mobility values at a drain voltage of 0.1 V and plot the on current (when Vg=3 V) versus the low field electron mobility (in Excel or equivalent).

Record a sufficient range and number of mobility points to create a useful graph.

(b)  Repeat for a drain voltage of 3 V.

(c)   Discuss how the concept of velocity saturation in MOSFETs can explain the trends observed in your graphs, commenting on:

i.       why on current initially increases linearly with mobility but then saturates at higher mobilities.

ii.       why this saturation occurs at lower mobilities for the higher drain voltage.

Part II for ELEC6256 students     Electronic Band Structure and Flat Band Conditions

***Only for students taking ELEC6256***

(a)  Continuing with the mos1ex01.in example script, alter the script. to replace the process

simulation (Athena) with its structure file so that you do not have to re-run that part of the simulation over and over again (see helpful hint 2). Then follow helpful hint 3 to alter the script. so that conduction and valence band potentials are saved to the structure file and the structure file is plotted under zero bias conditions. Run the script, then use cutline to plot the conduction band, valence band and Fermi level (Electron QFL) from the gate, through the gate oxide and into the silicon substrate. Explain why:

i.       band bending is present in the silicon substrate, even with no voltage applied to the gate.

ii.       the simulation does not show the band structure for silicon in the polysilicon gate region.

(b)  Ramp the gate voltage to find the voltage required to achieve flat bands. Plot the resulting electronic band structure.

(c)  Vary the work function of the gate (see helpful hint 4), then ramp the gate voltage to

determine the voltage required to achieve flat bands at each work function value. Plot the flat band voltage against the gate work function (in Excel or equivalent) and explain the trend observed and the significance of the x axis intercept value.

Part III MOSFET Scaling

***For all students***

Take the example file mos1ex15.in as a starting point, and scale the gate length by changing the “cd” parameter in the Athena part of the code (see helpful hint 5). At what gate length does the source to drain leakage become too high? Change other process parameters, such as oxide thickness, doping concentration of the body, source and drain etc. such that the transistor parameters improve. Take the scaling parameters described in the ITRS Roadmap from the mid 2000s as starting point (see lecture notes). This part of the assignment is designed to be more open ended and to allow you to use your newly-acquired Silvaco TCAD simulation skills to tackle a real-world problem.

Report

The results of your work on the simulation tasks should be presented in a report and submitted as a PDF file via handin.ecs.soton.ac.uk by 4 pm on Wednesday 3rd December 2025.

The report should be structured as follows and should not exceed 12 pages including figures, references and appendices.

Part I

(a)  Electrical parameter extraction (methods and results)

(b)  Physical device parameter extraction (methods and results)

(c)  On current with drain voltage at 3V (method and result)

(d)  Theoretical MOSFET parameters (methods and results)

(e)  Comparison between calculated and extracted electrical parameters

Part II ELEC3207 only

(a)  Plot of Ion vs. low field electron mobility for Vd= 0.1 V

(b)  Plot of Ion vs. low field electron mobility for Vd= 3 V

(c)   Discussion/explanation of results

Part II ELEC6256 only

(a)  Plot of electronic band structure and explanation

(b)  Plot electronic band structure in flat band conditions and give the value of VFB.

(c)   Plot VFB vs. gate workfunction and explain x intercept value.

Part III

(method, results and discussion from device scaling investigation)

A template is available on the module’s Blackboard site.