COMP2120/CSIS1120 Computer Organization
Date: May 17, 2016
Question 1 (20%)
(a) Complete the fol lowing truth table for a 2-to-4 decoder. (4%)
(b) Draw a logic circuit for the 2-to-4 decoder in (a). (6%)
(c) Illustrate how we can use 2-to-4 decoder to construct 1 K-byte memory using four 256 x 8 bit RAM chips. (6%)
(d) Illustrate how we can use 2-to-4 decoder to construct a single bit 1-to-4 demultiplexer. (4%)
Question 2 (20%)
(a) Find the following sums/differences using 8-bit twos complement arithmetic. (8%)
(i) 67 + 58
(ii) 76 + 64
(iii) (-42) - 88
(iv) (-21) + (-35)
(b) Indicate which operations in (a) resulted in overflow, and state the overflow rule. (5%)
(c) Draw a flow chart for division algorithm, assuming three registers A, M, Qare available and the divisor is placed in the M register, and the dividend in the Q register. (5%)
(d) State the rule for assigning the signs of quotient and remainder when negative numbers are involved in the division operation. (2%)
Question 3 (20%)
(a) Explain in one sentence why cache is introduced between CPU and Main Memory (2%)
(b) State the Principle of Locality and explain why it is important to cache operations (5%)
(c) Describe and compare the following two techniques for mapping memory blocks into cache lines (3%)
(i) Direct
(ii) Associative
(d) Explain how Set Associative Mapping combines the strengths of both direct and associative approaches while reducing their disadvantages. (5%)
(e) For a system with two levels of cache, define Tc1 as the first-level cache access time; Tc2 as second-level cache access time; Tm = memory access time; H1 = first-level cache hit ratio; H2 =combined first/second level cache hit ratio. Provide an equation for the access time Ta for a read operation. (5%)
Question 4 (20%)
Consider a simple computer below. Except for PC and MAR, which are 12-bits registers, all other registers are 16 bits in width.
This simple computer has 16-bit instructions shown in the following table:
(a) Name and describe in one sentence the use of the each of the following registers. (5%)
i. PC
ii. MAR
iii. MOR
iv. IR
v. ACC
(b) Determine the size of the addressable memory space. (1 %)
(c) Describe the data flow between registers during instruction fetch cycle. (4%)
(d) Write the assembly program that calculate and display the sum of the first n integers, where n is the number acquired from the keypad. (10%)
Question 5 (20%)
(a) Compare the Programmed 1/0, Interrupt-Driven 110 and OMA techniques by complete the following table: (3%)
(b) List three differences between Memory Mapped 110 and Isolated 1/0 approaches (6%)
(c) Describe three different techniques for device identifications when multiple interrupts occur. (6%)
(d) Modify the following Instruction Cycle State Diagram to include interrupt cycle processing. (3%)
(e) Briefly explain the cycle stealing mechanism in OMA operation. (2%)