EEC 210
HW 4
1. Calculate the output resistance of the circuit below assuming that IIN = 100 µA and the devices have drawn dimensions of 100 µm/1 µm. Use the process parame- ters given in Table 2.4 at the end of this homework, and assume that Xd = 0 for all devices. Also, ignore the body effect for simplicity. Compare your answer with a SPICE simulation and also use SPICE to plot the IOUT - VOUT characteristic for VOUT from 0 to 3 V.
2. Design the circuit below to satisfy the following constraints:
(a) Transistor M2 must operate in the active region for values of VOUT to within 0.2 V of ground.
(b) The output current must be 50 µA.
(c) The output current must change less than 0.02 percent for a 1 V change in the output voltage.
Ignore the body effect for simplicity. Make all devices identical except for M4 . Use SPICE to check your design and also to plot the IOUT - VOUT characteristic for VOUT from 0 to 3 V.
3. Calculate the small-signal voltage gain of the common-source amplifier with active load below. Assume that VDD = 3 V and that all the transistors operate in the active region. Do the calculations for values of IREF of 1 mA, 100 µA, 10 µA, and 1 µA. Assume that the drawn dimensions of each transistor are W = 100 µm and L = 1 µm. Assume Xd = 0 and use Table 2.4 at the end of this homework for other parameters.
(a) At first, assume the transistors operate in strong inversion in all cases.
(b) Repeat part (a) including the effects of weak inversion. Use (1.253) with n = 1. 5 to calculate the transconductance of M1 . In case you do not have the
book, this equation gives gm = nVT/ID , which means that the transconductance
of an MOS transistor operating in weak inversion is identical to that of a cor- responding bipolar transistor except for the factor 1/n, which models the fact that the gate controls the surface potential indirectly. Assume that a transistor operates in weak inversion when its overdrive is less than 2n VT , which is about 78 mV at room temperature with n = 1. 5.
(c) Use SPICE to check your calculations for both parts (a) and (b).
VDD
4. Calculate the small-signal voltage gain of the common-source amplifier with deple- tion load below, including both the body effect and channel-length modulation. Assume that VDD = 3 V and that the dc input voltage is adjusted so that the dc out- put voltage is 1 V. Assume that M1 has drawn dimensions of W = 100 µm and L = 1 µm. Also, assume that M2 has drawn dimensions of W = 10 µm and L = 1 µm. For both transistors, assume that Xd = 0. For M2 , assume Vt0 = − 1 V. Also, ignore channel-length modulation when calculating the dc bias current, but include channel-length modulation when doing the small-signal analysis. Use Ta- ble 2.4 at the end of this homework for other parameters of both transistors.
TABLE 2.4 Summary of Process Parameters for a Typical Silicon-Gate n-Well CMOS Process with 0.4 m Minimum Allowed Gate Length
|
Parameter
|
Symbol
|
Value
n-Channel Transistor
|
Value
p-Channel Transistor
|
Units
|
|
Substrate doping
|
NA ND
|
5 1015
|
4 1016
|
Atoms/cm3
|
|
Gate oxide thickness
|
tox
|
80
|
80
|
Angstroms
|
|
Metal-silicon work function
|
φ
|
0 6
|
0 1
|
V
|
|
Channel mobility
|
;
|
450
|
150
|
cm2/V-sec
|
|
Minimum drawn channel length
|
drwn
|
0.4
|
0.4
|
m
|
|
Source, drain junction depth
|
Xj
|
0.15
|
0.18
|
m
|
|
Source, drain side diffusion
|
Ld
|
0.09
|
0.09
|
m
|
|
Overlap capacitance per unit gate width
|
Col
|
0.35
|
0.35
|
fF/ m
|
|
Threshold adjust implant (box dist)
|
|
|
|
|
|
impurity type
|
|
P
|
P
|
|
|
effective depth
|
Xi
|
0.16
|
0.16
|
m
|
|
effective surface concentration
|
Nsi
|
4 1016
|
3 1016
|
Atoms/cm3
|
|
Nominal threshold voltage
|
Vt
|
0.6
|
0 8
|
V
|
|
Polysilicon gate
|
dpoly
|
1020
|
1020
|
Atoms/cm3
|
|
doping concentration
|
|
|
|
|
|
Poly gate sheet resistance
|
Rs
|
5
|
5
|
Ω/□
|
|
Source, drain-bulk
|
Cj0
|
0.2
|
0.4
|
fF/ 2
|
|
junction capacitances (zero bias)
|
|
|
|
|
|
Source, drain-bulk junction
|
n
|
0.5
|
0.4
|
|
|
capacitance grading coefficient
|
|
|
|
|
|
Source, drain periphery capacitance (zero bias)
|
Cjsw0
|
1.2
|
2.4
|
fF/ m
|
|
Source, drain periphery
|
n
|
0.4
|
0.3
|
|
|
capacitance grading coefficient
|
|
|
|
|
|
Source, drain junction built-in potential
|
ψ
|
0.7
|
0.7
|
V
|
|
Surface-state density
|
QSS q
|
1011
|
1011
|
Atoms/cm2
|
|
Channel-length
|
|
0.02
|
0.04
|
m/V
|
|
modulation parameter
|
|
|
|
|