ENGR228-Digital Electronics
Independent Design Project
This project will involve the development and simulation of a Parallel-to-Serial and Serial-to-Parallel converter in VHDL. Digital systems often take parallel bytes of data and transmit them over a single wire to save on wire area, reduce crosstalk effects, increase clock speed, or to maintain compatibility between devices. The exercise will introduce component instantiation and the use of multiple VHDL module files within a single project. When designing complicated systems in VHDL, it is good and common practice to disseminate the functioning blocks of the system over several VHDL modules, thus increasing the ease and functionality of the code.
The schematic of the whole system is shown in Fig. 1. Different VHDL modules, entities, components, ports and signals of this figure might be confusing at first so it is important to understand the hierarchy before beginning the exercise. In this lab we will be using a counter, a serialization converter and a de-serialization converter. The counter is used to control the rate and the timing at which we place or remove data to and from the serial line and will be a component of the serialization entities. To achieve this aim you are supposed to complete the following sequence of tasks.
1. Create a new Quartus Prime project and call the project Lab_1. First we will create a 4-bit counter that will act as a timer for the serialization and de-serialization modules. Add a new VHDL file to the project. Name this module counter. Refer to the previous lab for guidance if necessary. Create a test bench to check the functionality of your code.
2. Once you are assured the counter is working properly create a new VHDL module called parallelToSerial in the same way that you created the counter. In this module we design this entity to take an 8-bit parallel input signal and convert it into a serial output format such that each bit will be transmitted on a 1-bit wide output wire over 8 clock cycles. In order to time the transfer, we will use the counter module that we created earlier. The parallelToSerial module should have an 8-bit input port, aclk input and a singlestd_logic serial output.
3. In order to sort out the required timing for the parallel-to-serial conversion, the counter created in part 1 can be instantiated within this module. In this piece of code, we effectively create a state machine by defining different binary patterns and using a case statement to switch between the states. Given that the counter module has 16 possible states, and it counts up sequentially on its count port, we can switch between different cases on each binary count. For instance:
state 1, “0001”: we take the first parallel bit, input_port(0), and place it on the serial output port, output_port.
state 2, “0010”: we put the second bit, input_port(1), on the output and soon.
4. Once you have created the conversion code, generate a test bench that loads the parallel input port with the byte “01010101” as stimulus and no initial delays, to ensure that the code is working correctly and observe the serial output over 8 cycles.
5. The last step is creation of the de-serialization module by adding a new VHDL Module called serialToParallel. This will be nearly identical to the parallelToSerial module, except you will be assigning the current bit value on the serial input wire onto a different parallel output bit in each sequential case statement provided by the counter signal. To prevent the output port from presenting incomplete data a separate signal should be defined to load the parallel output signal to the physical output port after 8 bits have been assigned. Once you have generated the VHDL module, copying the behavioral description of parallelToSerial may be a good start. Verify your design in simulation. Create a test bench and load the serial input line as follows:
Process begin
wait until clk_input = '1';
wait for clk_period;
data_input <= ‘0’;
wait for clk_period;;
data_input <= ‘0’;
wait for clk_period;
data_input <= ‘0’;
wait for clk_period;
data_input <= ‘0’;
wait for clk_period;
data_input <= ‘0’;
wait for clk_period;
data_input <= ‘ 1’;
end process;
6. Now you have a serialization, de-serialization and counter module in your project with individual test benches. The next step is to create yet another VHDL module called combination, which will connect the two serialization modules you have created. This way you can create a test bench that will load the 8-bit parallel input of the module combination and be transferred to the input of the parallelToSerial module. The data packet will be serialized and then sent out on a signal that is connected to the serialToParallel module. This packet will be recreated as a parallel signal and sent out on the 8-bit output port of the combined module as shown in Fig. 1.
Figure 1. Combining Serial to Parallel and Parallel to Serial modules in one VHDL module named Combination.
The combination module needs a common clk port, and 8-bit input and 8-bit output parallel ports. Instantiate the parallelToSerial and serialToParallel modules. Then you simply need to create signals that connect the input of the combination module to the input of the parallelToSerial module, the output of that module to the input of the serialToParallel module and finally the output of that module to the output port of the combination.
7. Once this is done, create the test bench for the combination module that simply gives the input port two consecutive 8-byte data “01010101” and “11000101” which should be observed each at the output port 8-clock cycles later.